View LVCMOS25_8595269.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds553 (v1.1) may 5, 2007 www.xilinx.com 1 product specification ? 2006, 2007 xilinx, inc. all rights reserved. all xilinx tradem arks, registered trademarks, patents, and disclaimers are as li sted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? aec-q100 device qualification and full ppap support available in both i-grade and extended temperature q-grade ? guaranteed to meet full electrical specifications over t a = -40 c to +105 c with t j maximum = +125 c (q-grade) ? optimized for 1.8v systems ? industry?s best 0.18 micron cmos cpld - optimized architecture for effective logic synthesis - multi-voltage i/o operation ? 1.5v to 3.3v ? available in the following package options - 44-pin vqfp with 33 user i/o - 100-pin vqfp with 64 user i/o - pb-free only for all packages ? advanced system features - fastest in system programming 1.8v isp using ieee 1532 (jtag) interface - ieee1149.1 jtag boundary scan test - optional schmitt-trigger input (per pin) - two separate i/o banks - realdigital? 100% cmos product term generation - flexible clocking modes optional dualedge triggered registers - global signal options with macrocell control multiple global clocks with phase selection per macrocell multiple global output enables global set/reset - efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - advanced design security - optional bus-hold, 3-state or weak pullup on selected i/o pins - open-drain output option for wired-or and led drive - optional configurable grounds on unused i/os - mixed i/o voltages compatible with 1.5v, 1.8v, 2.5v, and 3.3v logic levels - pla architecture superior pinout retention 100% product term routability across function block - hot pluggable refer to the coolrunner?-ii automotive cpld family data sheet for architecture description. warning: programming temperature range of t a = 0 c to +70 c. description the coolrunner-ii automotive 64-macrocell device is designed for both high performance and low power applica- tions. this lends power savings to high-end communication equipment and high speed to battery operated devices. due to the low power stand-by and dynamic operation, overall system reliability is improved this device consists of four function blocks inter-con- nected by a low power advanced interconnect matrix (aim). the aim feeds 40 true and complement inputs to each function block. the function blocks consist of a 40 by 56 p-term pla and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. additionally, these registers can be globally reset or preset and configured as a d or t flip-flop or as a d latch. there are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. a schmitt trigger input is available on a per input pin basis. in addition to stor- ing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. clocking is available on a global or function block basis. three global clocks are available for all function blocks as a synchronous clock source. macrocell registers can be individually configured to power up to the zero or one state. a global set/reset control line is also available to asynchro- nously set or reset selected registers during operation. additional local clock, synchronous clock-enable, asynchro- nous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function block basis. a dualedge flip-flop feature is also available on a per mac- rocell basis. this feature allows high performance synchro- nous operation based on lower frequency clocking to help reduce the total power consumption of the device. the coolrunner-ii automotive 64-macrocell cpld is i/o compatible with standard lvttl and lvcmos18, LVCMOS25, and lvcmos33 (see table 1 ). this device is 0 xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 00 product specification r
xa2c64a coolrunner-ii automotive cpld 2 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r also 1.5v i/o compatible with the use of schmitt-trigger inputs. another feature that eases voltage translation is i/o bank- ing. two i/o banks are available on the coolrunner-ii auto- motive 64-macrocell device that permit easy interfacing to 3.3v, 2.5v, 1.8v, and 1.5v devices. realdigital design technology xilinx coolrunner-ii automotive cplds are fabricated on a 0.18 micron process technology which is derived from lead- ing edge fpga product development. coolrunner-ii auto- motive cplds employ realdigital, a design technique that makes use of cmos technology in both the fabrication and design methodology. realdigital design technology employs a cascade of cmos gates to implement sum of products instead of traditional sense amplifier methodology. due to this technology, xilinx coolrunner-ii automotive cplds achieve both high performance and low power oper- ation. supported i/o standards the coolrunner-ii automotive 64-macrocell features both lvcmos and lvttl i/o implementations. see ta b l e 1 for i/o standard voltages. the lvttl i/o standard is a general purpose eia/jedec standard for 3.3v applications that use an lvttl input buffer and push-pull output buffer. the lvcmos standard is used in 3.3v, 2.5v, 1.8v applications. coolrunner-ii automotive cplds are also 1.5v i/o com- patible with the use of schmitt-trigger inputs. table 1: i/o standards for xa2c64a iostandard attribute output v ccio input v ccio lvttl 3.3 3.3 lvcmos33 3.3 3.3 LVCMOS25 2.5 2.5 lvcmos18 1.8 1.8 lvcmos15 (1) 1.5 1.5 (1) lvcmos15 requires schmitt-trigger inputs. figure 1: i cc vs frequency table 2: i cc vs frequency (lvcmos 1.8v t a = 25c) (1) frequency (mhz) 0 25 50 75 100 150 typical i cc (ma) 0.017 1.8 3.7 5.5 7.48 11.0 notes: 1. 16-bit up/down, resetable binary counter (one counter per function block). frequency (mhz) ds553_01_092106 i cc (ma) 0 0 10 5 15 150 100 50
xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 www.xilinx.com 3 product specification r recommended operating conditions dc electrical characteristics (over recommended operating conditions) absolute maximum ratings symbol description value units v cc supply voltage relative to ground ?0.5 to 2.0 v v ccio supply voltage for output drivers ?0.5 to 4.0 v v jtag (2) jtag input voltage limits ?0.5 to 4.0 v v ccaux jtag input supply voltage ?0.5 to 4.0 v v in (1) input voltage relative to ground (1) ?0.5 to 4.0 v v ts (1) voltage applied to 3-state output (1) ?0.5 to 4.0 v v stg (3) storage temperature (ambient) ?65 to +150 c t j junction temperature +125 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easiest to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +4.5v, provided this over or undershoot lasts less than 10 ns and with t he forcing current being limited to 200 ma. 2. valid over commercial temperature range. 3. for soldering guidelines and thermal considerations, see the device packaging information on the xilinx website. for pb free packages, see xapp427 . symbol parameter min max units v cc supply voltage for internal logic and input buffers industrial t a = ?40c to +85c 1.7 1.9 v q-grade t a = -40 c to +105 c t j maximum = +125 c 1.7 1.9 v v ccio supply voltage for output drivers @ 3.3v operation 3.0 3.6 v supply voltage for output drivers @ 2.5v operation 2.3 2.7 v supply voltage for output drivers @ 1.8v operation 1.7 1.9 v supply voltage for output drivers @ 1.5v operation 1.4 1.6 v v ccaux jtag programming pins 1.7 3.6 v symbol parameter test conditions typical max. units i ccsb standby current industrial v cc = 1.9v, v ccio = 3.6v 43 165 a i ccsb standby current q-grade v cc = 1.9v, v ccio = 3.6v 43 700 a i cc (1) dynamic current f = 1 mhz - 1.50 ma f = 50 mhz - 7 ma c jtag jtag input capacitance f = 1 mhz - 10 pf c clk global clock input capacitance f = 1 mhz - 12 pf c io i/o capacitance f = 1 mhz - 10 pf i il (2) input leakage current v in = 0v or v ccio to 3.9v - +/?10 a i ih (2) i/o high-z leakage v in = 0v or v ccio to 3.9v - +/?10 a notes: 1. 16-bit up/down, resetable binary counter (one counter per function block) tested at v cc =v ccio = 1.9v.
xa2c64a coolrunner-ii automotive cpld 4 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r lvcmos 3.3v and lvttl 3.3v dc voltage specifications lvcmos 2.5v dc voltage specifications 1. the v ih max value represents the jedec specification for LVCMOS25. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. symbol parameter test conditions min. max. units v ccio input source voltage 3.0 3.6 v v ih high level input voltage 2 3.9 v v il low level input voltage ?0.3 0.8 v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 3v v ccio ? 0.2v - v v ol low level output voltage, industrial grade i ol = 8 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v low level output voltage, q-grade i ol = 4 ma, v ccio = 3v - 0.4 v i ol = 0.1 ma, v ccio = 3v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage 2.3 2.7 v v ih high level input voltage 1.7 v ccio + 0.3 (1) v v il low level input voltage ?0.3 0.7 v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 2.3v v ccio ? 0.4v - v i oh = ?0.1 ma, v ccio = 2.3v v ccio ? 0.2v - v v ol low level output voltage, industrial grade i ol = 8 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v low level output voltage, q-grade i ol = 4 ma, v ccio = 2.3v - 0.4 v i ol = 0.1 ma, v ccio = 2.3v - 0.2 v
xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 www.xilinx.com 5 product specification r lvcmos 1.8v dc voltage specifications 1. the v ih max value represents the jedec specification for lvcmos18. the coolrunner-ii input buffer can tolerate up to 3.9v without physical damage. lvcmos 1.5v dc voltage specifications (1) schmitt trigger input dc voltage specifications symbol parameter test conditions min. max. units v ccio input source voltage - 1.7 1.9 v v ih high level input voltage - 0.65 x v ccio v ccio + 0.3 (1) v v il low level input voltage - ?0.3 0.35 x v ccio v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 1.7v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.7v v ccio ? 0.2 - v v ol low level output voltage, industrial grade i ol = 8 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v low level output voltage, q-grade i ol = 4 ma, v ccio = 1.7v - 0.45 v i ol = 0.1 ma, v ccio = 1.7v - 0.2 v symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 1.6 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v v oh high level output voltage, industrial grade i oh = ?8 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v high level output voltage, q-grade i oh = ?4 ma, v ccio = 1.4v v ccio ? 0.45 - v i oh = ?0.1 ma, v ccio = 1.4v v ccio ? 0.2 - v v ol low level output voltage, industrial grade i ol = 8 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v low level output voltage, q-grade i ol = 4 ma, v ccio = 1.4v - 0.4 v i ol = 0.1 ma, v ccio = 1.4v - 0.2 v notes: 1. hysteresis used on 1.5v inputs. symbol parameter test conditions min. max. units v ccio input source voltage - 1.4 3.9 v v t+ input hysteresis threshold voltage - 0.5 x v ccio 0.8 x v ccio v v t- -0.2 x v ccio 0.5 x v ccio v
xa2c64a coolrunner-ii automotive cpld 6 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r ac electrical characteristics over recommended operating conditions symbol parameter -7 -8 units min. max. min. max. t pd1 propagation delay single p-term - 6.7 - 6.7 ns t pd2 propagation delay or array - 7.5 - 7.5 ns t sud direct input register clock setup time 3.3 - 3.3 - ns t su1 setup time (single p-term) 2.5 - 2.8 - ns t su2 setup time (or array) 3.3 - 3.6 - ns t hd direct input register hold time 0.0 - 0.0 - ns t h p-term hold time 0.0 - 0.0 - ns t co clock to output - 6.0 - 6.0 ns f toggle (1) internal toggle rate (1) -300-300mhz f system1 (2) maximum system frequency (2) -159-152mhz f system2 (2) maximum system frequency (2) -141-135mhz f ext1 (3) maximum external frequency (3) -118-114mhz f ext2 (3) maximum external frequency (3) -108-104mhz t psud direct input register p-term clock setup time 1.7 - 1.7 - ns t psu1 p-term clock setup time (single p-term) 0.9 - 0.9 - ns t psu2 p-term clock setup time (or array) 1.7 - 1.7 - ns t phd direct input register p-term clock hold time 1.4 - 1.4 - ns t ph p-term clock hold 2.7 - 2.7 - ns t pco p-term clock to output - 8.4 - 8.4 ns t oe /t od global oe to output enable/disable - 10.0 - 10.0 ns t poe /t pod p-term oe to output enable/disable - 11.0 - 11.0 ns t moe /t mod macrocell driven oe to output enable/disable - 11.0 - 11.0 ns t pao p-term set/reset to output valid - 9.7 - 9.7 ns t ao global set/reset to output valid - 8.3 - 8.3 ns t suec register clock enable setup time 3.7 - 3.7 - ns t hec register clock enable hold time 0.0 - 0.0 - ns t cw global clock pulse width high or low 2.2 - 2.2 - ns t pcw p-term pulse width high or low 7.5 - 7.5 - ns t aprpw asynchronous preset/reset pulse width (high or low) 7.5 - 7.5 - ns t config (4) configuration time - 50.0 - 50 s notes: 1. f toggle is the maximum frequency of a dual edge triggered t flip-flop with output enabled. 2. f system (1/t cycle ) is the internal operating frequency for a device fully populated with 16-bit up/down, resetable binary counter (one counter per function block). 3. f ext (1/t su1 +t co ) is the maximum external frequency. 4. typical configuration current during t config is 2.3 ma.
xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 www.xilinx.com 7 product specification r internal timing parameters symbol parameter (1) -7 -8 units min. max. min. max. buffer delays t in input buffer delay - 2.4 - 2.4 ns t din direct data register input delay - 4.0 - 3.7 ns t gck global clock buffer delay - 2.5 - 2.5 ns t gsr global set/reset buffer delay - 3.5 - 3.5 ns t gts global 3-state buffer delay - 3.9 - 3.9 ns t out output buffer delay - 2.8 - 2.8 ns t en output buffer enable/disable delay - 6.1 - 6.1 ns p-term delays t ct control term delay - 2.5 - 2.5 ns t logi1 single p-term delay adder - 0.8 - 0.8 ns t logi2 multiple p-term delay adder - 0.8 - 0.8 ns macrocell delay t pdi input to output valid - 0.7 - 0.7 ns t ldi setup before clock (transparent latch) - 2.5 - 2.5 ns t sui setup before clock 1.8 - 2.1 - ns t hi hold after clock 0.0 - 0.0 - ns t ecsu enable clock setup time 1.3 - 1.3 - ns t echo enable clock hold time 0.0 - 0.0 - ns t coi clock to output valid - 0.7 - 0.7 ns t aoi set/reset to output valid - 2.0 - 2.0 ns feedback delays t f feedback delay - 3.0 - 3.0 ns t oem macrocell to global oe delay - 1.7 - 1.7 ns i/o standard time adder delays 1.5vcmos t hys15 hysteresis input adder - 6.0 - 6.0 ns t out15 output adder - 1.5 - 1.5 ns t slew15 output slew rate adder - 6.0 - 6.0 ns i/o standard time adder delays 1.8v cmos t hys18 hysteresis input adder - 4.0 - 4.0 ns t out18 output adder - 0.0 - 0.0 ns t slew output slew rate adder - 5.0 - 5.0 ns
xa2c64a coolrunner-ii automotive cpld 8 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r i/o standard time adder delays 2.5v cmos t in25 standard input adder - 0.6 - 0.7 ns t hys25 hysteresis input adder - 3.0 - 3.0 ns t out25 output adder - 0.9 - 1.0 ns t slew25 output slew rate adder - 5.0 - 5.5 ns i/o standard time adder delays 3.3v cmos/ttl t in33 standard input adder - 0.6 - 0.8 ns t hys33 hysteresis input adder - 3.0 - 3.0 ns t out33 output adder - 1.4 - 1.7 ns t slew33 output slew rate adder - 5.0 - 6.6 ns (1) 1.5 ns input pin signal rise/fall. internal timing parameters (continued) symbol parameter (1) -7 -8 units min. max. min. max.
xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 www.xilinx.com 9 product specification r switching characteristics ac test circuit typical i/o output curves figure 4: typical i/o output curves figure 2: derating curve for t pd figure 3: ac load circuit number of outputs switching 12 4 8 1 6 3.0 4.0 5.0 v cc = v ccio = 1.8v, t = 25 o c t pd2 (ns) 5.5 4.5 3.5 ds092_02_09230 2 r 1 v cc c l r 2 device under test output type lvttl33 lvcmos33 LVCMOS25 lvcmos18 lvcmos15 r 1 268 275 188 112.5 150 r 2 235 275 188 112.5 150 c l 35 pf 35 pf 35 pf 35 pf 35 pf ds092_03_09230 2 test point notes: 1. c l includes test fixtures and probe capacitance. 2. 1.5 nsec maximum rise/fall times on inputs. vo output volts i/o output current (ma) vdde 1 1.5 v 1.8 v 2.5 v 3.3 v
xa2c64a coolrunner-ii automotive cpld 10 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r pin descriptions function block macrocell vqg44 vqg100 i/o banking 1 1 38 13 bank 2 1 2 37 12 bank 2 133611bank 2 14-10bank 2 15-9bank 2 16-8bank 2 17-7bank 2 18-6bank 2 1(gts1) 9 34 4 bank 2 1(gts0) 10 33 3 bank 2 1(gts3) 11 32 2 bank 2 1(gts2) 12 31 1 bank 2 1(gsr) 13 30 99 bank 2 114-97bank 2 115-94bank 2 116-92bank 2 2 1 39 14 bank 1 2 2 40 15 bank 1 23-16bank 1 24-17bank 1 2 5 41 18 bank 1 2 6 42 19 bank 1 2(gck0) 7 43 22 bank 1 2(gck1) 8 44 23 bank 1 29-24bank 1 2(gck2) 10 1 27 bank 1 211-28bank 1 212229bank 1 213330bank 1 214-32bank 1 215-33bank 1 216-34bank 1
xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 www.xilinx.com 11 product specification r 3 1 29 91 bank 2 3 2 28 90 bank 2 3 3 27 89 bank 2 34-81bank 2 35-79bank 2 3 6 23 78 bank 2 37-77bank 2 38-76bank 2 39-74bank 2 3102272bank 2 3112171bank 2 3122070bank 2 313-68bank 2 3141967bank 2 3151864bank 2 316-61bank 2 41535bank 1 42636bank 1 43-37bank 1 44-39bank 1 45-40bank 1 46-41bank 1 47842bank 1 48-43bank 1 49-49bank 1 410-50bank 1 4111252bank 1 412-53bank 1 4131355bank 1 4141456bank 1 4151658bank 1 416-60bank 1 1. gts = global output enable, gsr = global set reset, gck = global clock. 2. gck, gsr, and gts pins can also be used for general purpose i/o. pin descriptions (continued) function block macrocell vqg44 vqg100 i/o banking
xa2c64a coolrunner-ii automotive cpld 12 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r xa2c64a global, jtag, power/ground and no connect pins ordering information pin type pc44 vq44 qfg48 cp56 vq100 tck 17 11 23 k10 48 tdi 15 9 21 j10 45 tdo 30 24 40 a6 83 tms 16 10 22 k9 47 v ccaux (jtag supply voltage) 41 35 3 d3 5 power internal (v cc ) power bank 1 i/o (v ccio1 ) power bank 2 i/o (v ccio2 ) 21 15 29 g8 26,57 13 7 19 h6 38, 51 32 26 42 c6 88, 98 ground 10, 23, 31 4,17,25 16, 31, 41 h4, f8, c7 21, 31, 62, 69, 84,100 no connects 20, 25, 44, 46, 54, 59, 63, 65, 66, 73, 75, 80, 82, 85, 86, 87, 93, 95, 96 total user i/o 33 33 37 45 64 device ordering no. and part marking no. pin/ball spacing ja (c/watt) jc (c/watt) package type package body dimensions i/o ind. (i) (1) hi-t (q) xa2c64a-7vqg44i 0.8mm 46.6 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 i xa2c64a-8vqg44q 0.8mm 46.6 8.2 very thin quad flat pack; pb-free 10mm x 10mm 33 q xa2c64a-7vqg100i 0.5mm 53.2 14.6 very thin quad flat pack; pb-free 14mm x 14mm 64 i xa2c64a-8vqg100q 0.5mm 53.2 14.6 very thin quad flat pack; pb-free 14mm x 14mm 64 q notes: 1. i = industrial (t a = ?40 c to +85 c); q = automotive ( t a = -40 c to +105 c with t j maximum = +125 c ). pb- free example: xa2c64a vq g 44 i device speed grade package type pb -free number of pins -7 temperature range
xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 www.xilinx.com 13 product specification r device part marking figure 5: sample package with part marking package pinout diagrams part marking for non-chip scale package xa2cxxx vqg44 7 i device type package speed operating range this line not related to device part number r part marking for non-chip scale package figure 6: vqg44 package vqg44 top view i/o (1) i/o (1) i/o (1) i/o (3) i/o i/o i/o v ccio2 gnd tdo i/o i/o (2) i/o (2) i/o i/o i/o i/o i/o i/o i/o v aux i/o (1) i/o i/o i/o v cc i/o gnd i/o i/o i/o i/o i/o i/o (2) i/o i/o gnd i/o i/o v ccio1 i/o tdi tms tck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 (1) - global output enable (2) - global clock (3) - global set/reset
xa2c64a coolrunner-ii automotive cpld 14 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r coolrunner-ii automotive requirements and recommendations requirements the following requirements are for all automotive applica- tions: 1. use a monotonic, fast ramp power supply to power up coolrunner-ii . a v cc ramp time of less than 1 ms is required. 2. do not float i/o pins during device operation. floating i/o pins can increase i cc as input buffers will draw 1-2 ma per floating input. in addition, when i/o pins are floated, noise can propagate to the center of the cpld. i/o pins should be appropriately terminated with bus-hold or pull-up. unused i/os can also be configured as c gnd (programmable gnd). 3. do not drive i/o pins without v cc /v ccio powered. 4. sink current when driving leds. because all xilinx cplds have n-channel pull-down transistors on outputs, it is required that an led anode is sourced through a resistor externally to v cc . consequently, this will give the brightest solution. 5. avoid pull-down resistors. always use external pull-up resistors if external termination is required. this is because the coolrunner-ii automotive cpld, which includes some i/o driving circuits beyond the input and output buffers, may have contention with external pull-down resistors, and, consequently, the i/o will not switch as expected. 6. do not drive i/os pins above the v ccio assigned to its i/o bank. a. the current flow can go into v ccio and affect a user voltage regulator. b. it can also increase undesired leakage current associated with the device. figure 12: vq100 package vqg100 top view gnd i/o (3) v ccio2 i/o nc nc i/o nc i/o i/o i/o i/o v ccio2 nc nc nc gnd tdo nc i/o nc i/o i/o i/o i/o v cc i/o (2) i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o v ccio1 i/o i/o i/o i/o i/o nc tdi nc tms tck i/o i/o nc i/o nc i/o i/o i/o gnd i/o i/o nc nc i/o nc gnd i/o i/o nc i/o vcc i/o i/o nc i/o i/o v ccio1 i/o (1) i/o (1) i/o (1) i/o (1) v aux i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc gnd i/o (2) i/o (2) i/o nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (1) - global output enable (2) - global clock (3) - global set/reset
xa2c64a coolrunner-ii automotive cpld ds553 (v1.1) may 5, 2007 www.xilinx.com 15 product specification r c. if done for too long, it can reduce the life of the device. 7. do not rely on the i/o states before the cpld configures. during power up, the cpld i/os may be affected by internal or external signals. 8. use a voltage regulator which can provide sufficient current during device power up. as a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a cpld in order to guarantee the cpld can configure successfully. 9. ensure external jtag terminations for tms, tck, tdi, tdo should comply with the ieee 1149.1. all xilinx cplds have internal weak pull-ups on tdi, tms, and tck. 10. attach all cpld v cc and gnd pins in order to have necessary power and ground supplies around the cpld. 11. decouple all v cc and v ccio pins with capacitors of 0.01 f and 0.1 f closest to the pins for each v cc /v ccio -gnd pair. 12. configure i/os properly. coolrunner-ii automotive cplds have i/o banks; therefore, signals must be assigned to appropriate banks (lvcmos33, lvcmos18 ?) recommendations the following recommendations are for all automotive appli- cations. 1. use strict synchronous design (only one clocking event) if possible. a synchronous system is more robust than an asynchronous one. 2. include jtag stakes on the pcb. jtag stakes can be used to test the part on the pcb. they add benefit in reprogramming part on the pcb, inspecting chip internals with intest, identifying stuck pins, and inspecting programming patterns (if not secured). 3. coolrunner-ii automotive cplds work with any power sequence, but it is preferable to power the v cci (internal v cc ) before the v ccio for the applications in which any glitches from device i/os are unwanted. 4. do not disregard report file warnings. software identifies potential problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. understand the timing report. this report file provides a speed summary along with warnings. read the timing file (*.tim) carefully. analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. review fitter report equations. equations can be shown in abel-like format, or can also be displayed in verilog or vhdl formats. the fitter report also includes switch settings that are very informative of other device behaviors. 7. let design software define pinouts if possible. xilinx cpld software works best when it selects the i/o pins and manages resources for users. it can spread signals around and improve pin-locking. if users must define pins, plan resources in advance. 8. perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. distribute ssos (simultaneously switching outputs) evenly around the cpld to reduce switching noise. 10. terminate high speed outputs to eliminate noise caused by very fast rising/falling edges. automotive warranty disclaimer this warranty does not extend to any implementation in an application or environment that is not contained within xilinx specifications. pro ducts are not designed to be fail-safe and are not warranted for use in the deployment of ai rbags. further, products are not warranted for use in applications that affect control of the vehicle unless there is a fail-safe or redundancy feature and also a warning signal to the operator of the vehicle upon failure. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations governing limitations on product liability.
xa2c64a coolrunner-ii automotive cpld 16 www.xilinx.com ds553 (v1.1) may 5, 2007 product specification r additional information additional information is available for the following coolrunner-ii topics: ? xapp784: bulletproof cpld design practices ? xapp375: timing model ? xapp376: logic engine ? xapp378: advanced features ? xapp382: i/o characteristics ? xapp389: powering coolrunner-ii ? xapp399: assigning vref pins to access these and all application notes with their associ- ated reference designs, click the following link and scroll down the page until you find the document you want: coolrunner-ii data sheets and application notes device packages revision history the following table shows the revision history for this document. date version revision 10/31/06 1.0 initial xilinx release. 05/05/07 1.1 change to v ih specification for 3.3v, 2.5v and 1.8v lvcmos.

▲Up To Search▲

Price & Availability of LVCMOS25

	To Download LVCMOS25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .